Speech Compression FPGA Design by Using Different Discrete Wavelet Transform Schemes

Compared with the traditional digital signal processor, the field programmable gate array (FPGA) has advantages of configurable datapath, low cost, reprogrammability, and high performance. As a result, the FPGA device becomes more and more popular in the field of digital signal processing applications. This paper presents FPGA design of speech compression by using different discrete wavelet transform (DWT) schemes including the Daubechies DWT and the Daubechies lifting scheme DWT. In this design work, the audio CODEC chip is used to convert analog speech into the digital format. The digital streams can either be stored inside the SDRAM for DWT postprocessing or compressed in real time by using the Daubechies lifting scheme DWT. The low pass filtering part of the DWT result represents the compressed speech. It can be read back from the SDRAM, converted to analog signal and then played clearly in speakers after upsampling is performed.