DocumentCode
3298281
Title
A 1.8 V continuous-time delta-sigma modulator with 2.5 MHz bandwidth
Author
Zhang, Yi ; Leuciuc, Adrian
Author_Institution
Dept. of Electr. & Comput. Eng., State Univ. of New York, Stony Brook, NY, USA
Volume
1
fYear
2002
fDate
4-7 Aug. 2002
Abstract
This paper describes the implementation of a low-voltage, wide bandwidth, continuous-time low-pass ΔΣ modulator. The presented modulator operates at a supply voltage of 1.8 V and can achieve a maximum SNDR of 74 dB (more than 12 bits) for an oversampling ratio of 32 and in a bandwidth of 2.5 MHz.
Keywords
continuous time systems; low-power electronics; sigma-delta modulation; 1.8 V; 2.5 MHz; SNDR; continuous-time delta-sigma modulator; low-pass ΔΣ modulator; low-voltage modulator; oversampling ratio; Bandwidth; CMOS process; Clocks; Delta modulation; Filters; Jitter; Noise shaping; Operational amplifiers; Signal to noise ratio; Switched capacitor circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN
0-7803-7523-8
Type
conf
DOI
10.1109/MWSCAS.2002.1187176
Filename
1187176
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