A 1.2 μm CMOS deadlock-free router for hypercycle networks

Author

Sivakumar, R. ; Dimopoulos, N.J.

Author_Institution

Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada

Volume

1

fYear

1993

fDate

19-21 May 1993

Firstpage

153

Abstract

The authors consider deadlock-free routing in hypercycles, which are class of multidimensional graphs used for modeling interconnection networks. Hypercycles offer simple routing, and incremental expansion, variable diameter, enhanced fault-tolerance, and hence can be tailored specifically to the topology of a particular application. The authors consider the hardware implementation of a 1.2μm CMOS chip that implements deadlock preventing routing. The chip consists of about 20,000 transistors and has an expected throughput of 20 million decisions per second

Keywords

CMOS digital integrated circuits; data flow graphs; fault tolerant computing; multidimensional systems; multiprocessor interconnection networks; network routing; 1.2 micron; CMOS chip; deadlock-free routing; fault-tolerance; hardware implementation; hypercycle networks; incremental expansion; multidimensional graphs; Circuits; Hypercubes; Multiprocessor interconnection networks; Network topology; Registers; Robustness; Routing; Sufficient conditions; System recovery; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Computers and Signal Processing, 1993., IEEE Pacific Rim Conference on

Conference_Location

Victoria, BC

Print_ISBN

0-7803-0971-5

Type

conf

DOI

10.1109/PACRIM.1993.407199

Filename

407199