DocumentCode
3299037
Title
Simple and accurate comparator circuit
Author
Shima, Takeshi ; Miyoshi, Koujirou
Author_Institution
Fac. of Eng., Kanagawa Univ., Yokohama, Japan
Volume
1
fYear
2002
fDate
4-7 Aug. 2002
Abstract
The novel comparator circuit is proposed. Not only the cross-coupled transistors, but also the load transistors pair block with cross-coupled capacitors contribute to enhancing the latch operation. The mechanism is explained in detail. The load circuit of the input differential stage is designed to reduce the input referred offset deviation. The basic idea of this load circuit was proposed by Rui Itou and T. Shima (see Proc. of IEEE 44th MWS-CAS, OH, p.417-421, Aug., 2001) and the idea is modified to be applicable to the comparator. In this paper, simulated results are shown using the VDEC design environment.
Keywords
comparators (circuits); equivalent circuits; network analysis; VDEC design environment; comparator circuit; cross-coupled capacitors; cross-coupled transistors; input differential stage; latch operation; load transistors pair block; Calibration; Capacitors; Circuit simulation; Circuit topology; Equivalent circuits; Latches; Performance gain; Power dissipation; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN
0-7803-7523-8
Type
conf
DOI
10.1109/MWSCAS.2002.1187216
Filename
1187216
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