Title :
High-performance divider using redundant binary representation
Author :
Wang, Guoping ; Ozaydin, Murad ; Tull, Monte
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Oklahoma Univ., Norman, OK, USA
Abstract :
A high-performance iterative quadratic convergence fixed-point, real and complex number, divider circuit using a previously developed redundant binary inner-product processor core is presented. The intermediate quotient coefficients are kept in redundant binary (RB) form without converting back to normal binary numbers. A unified multiplier using redundant binary representation for both signed and unsigned numbers is investigated. Goldschmidt and Newton-Raphson division methods are compared and the mathematical equivalence of these two methods is provided.
Keywords :
Newton-Raphson method; convergence of numerical methods; dividing circuits; fixed point arithmetic; floating point arithmetic; logic design; redundant number systems; Goldschmidt division method; Newton-Raphson division method; RB numbers; complex number divider; division method equivalence; fixed-point divider; high-performance divider; intermediate quotient coefficients; iterative quadratic convergence divider circuit; multiplier; real number divider; redundant binary inner-product processor core; redundant binary representation; signed numbers; unsigned numbers; Algorithm design and analysis; Approximation algorithms; Circuits; Convergence; Delay; Encoding; Equations; Hardware; Iterative methods; Mathematics;
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
DOI :
10.1109/MWSCAS.2002.1187260
