Semi floating-gate S/H circuits

This paper presents a new proposal for implementing voltage mode sample and hold (S/H) for multiple valued (MV) circuits. The circuits have been implemented using recharged semi floating-gate (SFG) technique for conventional CMOS processes and follows a new SFG S/H latching scheme. The concept is similar to the SFG latch technique. Two circuits for on-chip interconnection of SFG and non-SFG circuits are proposed. One read-in circuit introducing the required interleaved SFG recharge voltage, and one readout circuit capable of restoring the non-interleaved multiple valued voltage. A chip with the proposed circuits has been fabricated in AMS 0.35 μm. Included is measured chip results verifying the operation.