Title :
Failure analysis of a low yield mixed-signal product due to Deep-Nwell fabrication process marginality
Author :
Chin, Aaron K Y ; Seah, P.H. ; Chow, F.L. ; Koh, C.Q. ; Heng, C.C.
Author_Institution :
Syst. on Silicon Manuf. Co. Pte. Ltd., Singapore, Singapore
Abstract :
CMOS Mixed-signal RF product low yield investigation led to the finding of Deep-Nwell (DNW) process and layout marginality. Low yield analysis was carried out by performing electrical failure analysis (EFA) and physical failure analysis (PFA) using junction stain technique. Both process and layout marginality in DNW were evaluated. Post DNW implant photoresist profile assessment has been identified as an effective method on high-energy implantation related process assessment. Possible solutions were proposed to resolve the low yield issue.
Keywords :
mixed analogue-digital integrated circuits; CMOS mixed-signal RF product low yield investigation; DNW implant photoresist profile assessment; Deep-Nwell fabrication process marginality; electrical failure analysis; high energy implantation related process assessment; junction stain technique; layout marginality; low yield analysis; low yield mixed-signal product; physical failure analysis; Circuits; Fabrication; Failure analysis; Implants; Leakage current; MOS devices; Radio frequency; Resists; Silicon; System-on-a-chip;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits (IPFA), 2010 17th IEEE International Symposium on the
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-5596-6
DOI :
10.1109/IPFA.2010.5532236
