Single-rail self-timed logic circuits in synchronous designs

This paper presents a self-timed scheme for dynamic single-rail logic integrated in a single phase clock design. A generalized completion detection for generation of self-timed signals from single-rail gates is described and we show a novel application of the redundancy of a SD-adder to ease the self-timed signal generation. Further we discuss a universal evaluation scheme to overcome the problem of only non-inverting functions with dynamic single-rail gates. The presented SD-adder was integrated in a synchronous scheme and combines the advantages of simple synthesis and clock distribution for synchronous designs with fastest evaluation. Self-timed schemes result in fastest latch-free structures and robustness against clock-skew. Further the single-rail scheme on gate-level yields lower power consumption and smaller circuits. The use of inverting and non-inverting single-rail gates makes the synthesis close to standard synthesis. Simulations for the redundant adder design show area and power savings of 40% and 30% compared to complementary DOMINO logic structure.