Drive current boosting and low sub-threshold swing obtained by δP+ layer in double-gate tunnel FET

Summary form only given: increasing short channel effects like drain induced barrier lowering (DIBL) and V<;sub>;T<;/sub>; roll-off are serious impediments to further scaling of conventional MOSFET. These limitations instigated all researchers to look for innovative devices. Non-scalable sub-threshold swing in MOSFET limits its application in high speed and low power application. Tunnel FET is a strong candidate in high speed and low power application because of its potential to get low Sub-Threshold swing (<;60 mv/dec). In the previous work it was demonstrated that silicon double gate tunnel FET (DGTFET) suffers from unacceptable low ON-current. Here we have shown that, by introducing the δ<;sub>;p<;/sub>;<;sup>;+<;/sup>; layer high ON-current (I<;sub>;ON<;/sub>;), low OFF-current (I<;sub>;OFF<;/sub>;) and very low subthreshold swing can be obtained in DGTFET. Schematic device structure is depicted. The 2D simulation carried out by using the Kane´s interband tunneling model. As doping profile is high band bending narrowing model is included. In both n-channel mode of operation and p-channel mode of operation conduction takes place by tunneling of electron from valance band of source to conduction band of drain region. Band to band tunneling is a strong function of electric field. Probability of tunneling becomes very significant when tunneling width reduces less than 10 nm. The simulated conduction band (E_C) and valance band (E_V) along the interface of Si-SiO₂, under various bias conditions. As VGS increases from 0-0.8 V band bending becomes significant and further tunnel width decreases as VDS is applied. In the regime of 100 nm channel length and 2 nm oxide thicknesses, the input characteristic of n-channel DGTFET. In the off state (V_GS<;0.2 V), current flows very low (<;10^-12 Amp/μm) and then tunneli- g current increases very sharply. From the input characteristic we can say that DGTFET is almost free from drain induced barrier lowering problem. After channel length scaling, OFF-current increases and there is no significant increase of ON-current is seen. But it shows the potential that up to 40 nm of channel length, OFF-current is acceptable according to ITRS requirement. DGTFET gets saturated at very low voltage of VDS (~ 0.2 V), as shown in output characteristic. Therefore leads to zero output conductance. The input characteristic of p-channel tunnel FET is shown. But in p-channel mode of operation sufficient band bending takes place at higher gate and drain voltage. As the channel is formed by holes, tunneling driving current is less compare to n-channel TFET. The ON-current can be improved by careful choice of dielectric material. It can be seen that by high dielectric constant material (like HfO₂) ON-current improves by two orders of magnitude. In n-channel operation threshold voltage V_T is 0.625 V (at 10^-7 Amp/μm), which is calculated by constant current method from the input characteristic. Very low point subthreshold swing (~ 28 mv/dec) is observed and because of that high I_ON/ I_OFF ratio (~10¹¹) is seen, which is useful to operate the device in low voltage range. In all low subthreshold swing, high I_ON/ I_OFF ratio and low V_T make this device a strong candidate for ultralow power and ultralow voltage application.