Bus-invert coding for LUT-based FPGAs

We describe an approximative implementation of bus-invert coding for LUT-based FPGAs driving an external bus through dual-data-rate outputs. The majority voter circuit, typically implemented as a tree of full-adders, is the performance-limiting unit, and is replaced by an inexact interval logic. For a 16-bit bus, logic depth is limited to five stages of 4-input LUTs. Compared to an adder-tree implementation, propagation delay of the inexact majority voter is approximately one half. The disadvantage is that signal transition statistic is suboptimal, and the maximum number of simultaneous signal changes is increased to 10 in rare cases.