Title :
A parallel algorithm for power estimation at gate level
Author :
Nourani, M. ; Nazarian, S. ; Afzali-Kusha, A.
Author_Institution :
Center for Integrated Circuits & Syst., Texas Univ., Richardson, TX, USA
Abstract :
In this paper we present an analytical method for estimating switching probability and power consumption of combinational circuits at the gate level. Considering the signal correlation and multiple-bit input switching, we propose an efficient scheme to estimate switching probability and dynamic power consumption of combinational CMOS circuits at the gate level accurately. Additionally, our algorithm has potential not to propagate the estimated values through the circuit and thus can be run in parallel machines for very large circuits.
Keywords :
CMOS logic circuits; combinational circuits; normal distribution; parallel algorithms; combinational CMOS circuits; combinational circuits; dynamic power consumption; gate level; multiple-bit input switching; parallel algorithm; parallel machines; power estimation; signal correlation; switching probability; Analytical models; CMOS technology; Circuit synthesis; Combinational circuits; Delay; Energy consumption; Equations; Parallel algorithms; Power dissipation; Switching circuits;
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
DOI :
10.1109/MWSCAS.2002.1187270
