Title :
A CAD suite for high-performance FPGA design
Author :
Hutchings, Brad ; Bellows, Peter ; Hawkins, Joseph ; Hemmert, Scott ; Nelson, Brent ; Rytting, Mike
Author_Institution :
Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
Abstract :
This paper describes the current status of a suite of CAD tools designed specifically for use by designers who are developing high-performance configurable-computing applications. The basis of this tool suite is JHDL, a design tool originally conceived as a way to experiment with Run-Time Reconfigured (RTR) designs. However, what began as a limited experiment to model RTR designs with Java has evolved into a comprehensive suite of design tools and verification aids, with these tools being used successfully to implement high-performance applications in Automated Target Recognition (ATR), sonar beamforming, and general image processing on configurable-computing systems
Keywords :
field programmable gate arrays; hardware description languages; logic CAD; reconfigurable architectures; CAD suite; CAD tools; JHDL; high-performance FPGA design; high-performance configurable-computing; Application software; Circuit simulation; Debugging; Design automation; Field programmable gate arrays; Hardware; Java; Runtime; Signal generators; Sonar navigation;
Conference_Titel :
Field-Programmable Custom Computing Machines, 1999. FCCM '99. Proceedings. Seventh Annual IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-7695-0375-6
DOI :
10.1109/FPGA.1999.803663
