Novel fault localization approach for ATPG / scan-fault failures in complex sub-nano FPGA/ASIC debugging

Author

Goh, L.L.

Author_Institution

Altera Corp. (M) Sdn. Bhd., Bayan Lepas, Malaysia

fYear

2010

fDate

5-9 July 2010

Firstpage

1

Lastpage

4

Abstract

Fault isolation in automated test pattern generation (ATPG) / scan-fault has been increasingly challenging in today´s advanced integrated circuit (IC) as diagnosis results usually point to extensive faulty nets which can be physically widespread on the die. This work highlights a novel approach in understanding electrical fault data with promising physical failure analysis (PFA) results in FPGA/ASIC debugging.

Keywords

application specific integrated circuits; failure analysis; fault diagnosis; field programmable gate arrays; FPGA/ASIC debugging; advanced integrated circuit; automated test pattern generation; electrical fault data; fault isolation; fault localization; physical failure analysis; scan-fault failure; Application specific integrated circuits; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Debugging; Failure analysis; Fault diagnosis; Field programmable gate arrays; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits (IPFA), 2010 17th IEEE International Symposium on the

Conference_Location

Singapore

ISSN

1946-1542

Print_ISBN

978-1-4244-5596-6

Type

conf

DOI

10.1109/IPFA.2010.5532246

Filename

5532246