Design and implementation of low power digital phase-locked loop

This paper proposes a low power architecture for second order digital phase-locked loop (DPLL). High power consumption of DPLL results from using a look-up table (LUT) in implementing the numerically controlled oscillator (NCO). A new design for NCO is presented in which no LUT is used. Proposed architecture implemented using field programmable gate array (FPGA) consumed 15.44 mw at 100 MHz clock frequency which means a more than 25% saving in power consumption compared to traditional NCO. Furthermore, proposed method also saves FPGA resources and works at faster clock frequency.