Efficient parallelisation of an MPEG-2 codec on a TMS320C80 video processor

Author

Cantineau, Olivier ; Legat, Jean-Didier

Author_Institution

Lab. de Microelectron., Univ. Catholique de Louvain, Belgium

fYear

1998

fDate

4-7 Oct 1998

Firstpage

977

Abstract

This paper presents an efficient implementation of an MPEG-2 video codec on a specialised digital signal processor, the TMS320C80 MVP. The parallelisation strategies involved in our work are overviewed, the system-level task distributions are presented and the low-level optimisations are described. The obtained encoder-decoder is able to encode CIF-format 4:2:0 colour intra- and P-pictures in real-time (25 Hz) with one motion vector per 16×16 macroblock

Keywords

circuit optimisation; code standards; digital signal processing chips; discrete cosine transforms; image colour analysis; image motion analysis; inverse problems; parallel architectures; telecommunication standards; transform coding; video codecs; 25 Hz; CIF-format; DCT; IDCT; MPEG-2 codec; TMS320C80 MVP; TMS320C80 video processor; colour P-pictures; colour intra-pictures; digital signal processor; efficient parallel implementation; encoder-decoder; low-level optimisations; motion vector; software pipeline; system-level task distributions; Decoding; Digital signal processing; Digital signal processors; Image coding; Laboratories; Microelectronics; Pipelines; Signal processing algorithms; Transform coding; Video codecs;

fLanguage

English

Publisher

ieee

Conference_Titel

Image Processing, 1998. ICIP 98. Proceedings. 1998 International Conference on

Conference_Location

Chicago, IL

Print_ISBN

0-8186-8821-1

Type

conf

DOI

10.1109/ICIP.1998.727413

Filename

727413