DocumentCode :
330029
Title :
A three Giga-op DSP chip for image processing
Author :
Redford, John
Author_Institution :
Pixel Magic Inc., Andover, MA, USA
fYear :
1998
fDate :
4-7 Oct 1998
Firstpage :
981
Abstract :
The PM48dx is a programmable image processor chip containing eight 32-bit data paths controlled by one instruction stream at an internal clock rate of 133 MHz. It uses 32-bit three-operand instructions. A single instruction can extract a bit field from a register, do multiply/accumulate on it, extract a bit field from the result, and then insert it into a another register. Instructions have deterministic timing to aid real-time applications. High memory bandwidth is supplied by external synchronous SRAMs. High IO bandwidth comes from two 32-bit ports with flexible, programmable control pins. The chip can achieve the equivalent of three billion 32-bit operations per second on real applications
Keywords :
SRAM chips; digital signal processing chips; image processing; parallel architectures; 3 GFLOPS; 32 bit; DSP chip; IO bandwidth; PM48dx; SIMD parallelism; bit field extraction; data paths; deterministic timing; image processing; instruction stream; internal clock rate; memory bandwidth; multiply/accumulate; programmable control pins; programmable image processor chip; real-time applications; register; synchronous SRAM; three-operand instructions; Bandwidth; Clocks; Data mining; Digital signal processing chips; Image processing; Pins; Programmable control; Registers; Streaming media; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Image Processing, 1998. ICIP 98. Proceedings. 1998 International Conference on
Conference_Location :
Chicago, IL
Print_ISBN :
0-8186-8821-1
Type :
conf
DOI :
10.1109/ICIP.1998.727414
Filename :
727414
Link To Document :
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