Total leakage reduction by observance of parameter variations

Leakage power dissipation and parameter variations are main topics in current research. The problem of parameter variations leads to modified timing analysis. Traditionally, this is done with corner-case simulations, which are quite conservative and pessimistic approaches. This paper proposes a new statistical static timing analysis (SSTA) to improve performance predictions. Furthermore, the developed SSTA and a dual-V_th/dual-T_ox CMOS (DTTCMOS) design technique are combined to reduce the total leakage within designs. Compared to traditional corner-case timing analyses the proposed approach reduces leakage by an average of 70% for raw designs and by an average of 25% in pre-optimized DTTCMOS designs.