A method for crosstalk fault detection in on-chip buses

At-speed testing of crosstalk induced logic and delay faults in core based SoCs, is becoming very important. Closely packed buses interconnecting cores are generally laid out on many interconnect layers to minimize area and delay. Aggressor-victim model is often used to represent the effect of crosstalk due to influence of one wire on the other. In this paper we propose an efficient method and corresponding BIST hardware for at-speed testing of such faults. The proposed BIST hardware is programmable and can provide a trade-off between test speed and test quality.