A comparative analysis of logic styles for secure IC´s against DPA attacks

This paper presents a comparative analysis of logic styles for secure IC´s against differential power analysis attacks. We have investigated the correlation between data and instantaneous power consumption in five logic styles including: static CMOS, single-ended domino, differential domino, charge recycling sense amplifier based logic, and dynamic current mode logic. Circuit simulations and statistical analysis show that dynamic current mode logic gives the lowest correlation between power consumption and data, while differential domino combined with a strict clocking scheme shows the best design complexity trade-off.