• DocumentCode
    3300544
  • Title

    Accelerating run-time reconfiguration on FCCMs

  • Author

    Heron, J.-P. ; Woods, R.F.

  • Author_Institution
    Sch. of Electr. & Electron Eng., Queen´´s Univ., Belfast, UK
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    260
  • Lastpage
    261
  • Abstract
    The paper describes the implementation of the arithmetic operations of multiplication, division and square root on a Xilinx XC6200 FPGA. By using a design approach to enhance similarities across circuits, partial reconfiguration has been used to allow reductions in reconfiguration times of up to 75% on trials using the VCC HOTWorks board
  • Keywords
    digital arithmetic; reconfigurable architectures; FCCMs; VCC HOTWorks board; Xilinx XC6200 FPGA; division; multiplication; run-time reconfiguration; square root; Acceleration; Arithmetic; Bismuth; Circuits; Equations; Field programmable gate arrays; Page description languages; Pattern matching; Radio access networks; Runtime;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field-Programmable Custom Computing Machines, 1999. FCCM '99. Proceedings. Seventh Annual IEEE Symposium on
  • Conference_Location
    Napa Valley, CA
  • Print_ISBN
    0-7695-0375-6
  • Type

    conf

  • DOI
    10.1109/FPGA.1999.803688
  • Filename
    803688
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3300544