Task-level partitioning and RTL design space exploration for multi-FPGA architectures

This paper presents SPADE, a system for partitioning designs onto multi-FPGA architectures. The input to SPADE is a task graph, that is composed of computational tasks, memory tasks and the communication and synchronization between tasks. SPADE consist of an iterative partitioning engine, an architectural constraint evaluator, and a throughput optimization and RTL design space exploration heuristic. We show how various architectural constraints can be effectively handled using an iterative partitioning engine