DocumentCode
3300679
Title
ICARUS: a dynamically reconfigurable computer architecture
Author
Baxter, Michael
Author_Institution
Ricoh Silicon Valley, Menlo Park, CA, USA
fYear
1999
fDate
1999
Firstpage
278
Lastpage
279
Abstract
ICARUS (Image Computing, Automatically Reconfigurable, Unlimited Scale), is an architecture for general purpose parallel computing. The current implementation uses standard FPGAs in novel ways, has no host CPU and differs in many ways from the “fixed CPU plus variable EPCA” approach to computing. Different instruction set architectures (ISAs) are loaded automatically during runtime. Two key architectural elements are S-Machines (Symbolic Machines), and T-Machines (Transaction Machines)
Keywords
parallel architectures; reconfigurable architectures; ICARUS; S-Machines; Symbolic Machines; T-Machines; Transaction Machines; parallel computing; reconfigurable computer architecture; standard FPGAs; Communication system control; Computer aided instruction; Computer architecture; Field programmable gate arrays; Hardware; Image segmentation; Instruction sets; Parallel processing; Runtime; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Field-Programmable Custom Computing Machines, 1999. FCCM '99. Proceedings. Seventh Annual IEEE Symposium on
Conference_Location
Napa Valley, CA
Print_ISBN
0-7695-0375-6
Type
conf
DOI
10.1109/FPGA.1999.803696
Filename
803696
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