Title :
Bezier curve rendering on VirtexTM
Author :
MacVicar, Donald ; Singh, Satnam ; Slous, Robert
Author_Institution :
Dept. of Comput. Sci., Glasgow Univ., UK
Abstract :
This report investigates how some of the new features in Xilinx´s Virtex FPGA may be use to support the efficient implementation of a graphics application via a synthesis flow. The principle new features that we investigate are BlockRAM, distributed RAM, special support for multiplication and the fully digital delay-locked loop (DLL) for controlling multiple clock domains
Keywords :
computer graphic equipment; field programmable gate arrays; random-access storage; rendering (computer graphics); Bezier curve rendering; BlockRAM; Xilinx Virtex FPGA; distributed RAM; fully digital delay-locked loop; graphics application; multiple clock domain control; multiplication; synthesis flow; Clocks; Delay; Equations; Field programmable gate arrays; Graphics; Iterative algorithms; Page description languages; Piecewise linear approximation; Read-write memory; Shape control;
Conference_Titel :
Field-Programmable Custom Computing Machines, 1999. FCCM '99. Proceedings. Seventh Annual IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-7695-0375-6
DOI :
10.1109/FPGA.1999.803712
