Influence of post-deposition annealing on metal-organic decomposed lanthanum cerium oxide film

The continuous downscaling of metal-oxide-semiconductor (MOS) based devices has triggered the efforts in looking for alternative gate oxides, which can substitute conventional silicon dioxide (SiO₂) as the gate oxide material. Various attempts had been devoted to utilizing high dielectric constant (k) gate oxides that are physically thick with similar equivalent oxide thickness (EOT). These include binary oxides like cerium oxide [1], lanthanum oxide [2-3], yttrium oxide [4], aluminium oxide [5-6], and ternary oxides, such as lanthanum hafnium oxide [7], lanthanum zirconium oxide [8], and lanthanum aluminium oxide [9]. Of these gate oxides, particularly lanthanum-based ternary oxides are of interest. This is because of the moisture absorption behavior of lanthanum oxide [10] that made a shift to use ternary based lanthanum oxide to cope with the problem. The beneficial effects demonstrated by lanthanum based ternary oxides have motivated the investigation on lanthanum cerium oxide, which has not been widely utilized as a gate oxide material. To the best of our knowledge, lanthanum cerium oxide had been used as a thermal barrier coating material. Recently, physical characteristics of lanthanum cerium oxide have been studied on Si by varying post-deposition annealing temperature (400, 600, 800, and 1000°C) at 15 min dwell time and varying annealing time from 15 to 120 min at 1000°C [11]. However, the MOS characteristics of lanthanum cerium oxide film have not been extensively investigated. Therefore, in this work, effects of post-deposition annealing temperature (600, 800, and 1000°C) carried out in Ar ambient for 90 min are examined on the physical and electrical characteristics of metal-organic decomposition derived lanthanum cerium oxide film spin-coated on Si substrate. Four diffraction peaks associated with (200), (220), (311), and (222) cubic phases of La_xCe_yO_z were detected in samples annealed- from 600 to 1000°C [Figure 1]. An additional peak associated to La₂Si₂O₇ was detected at (151) plane at 1000°C, indicating the formation of interfacial layer (IL). This IL had contributed to a reduction of effective oxide charge (Q_eff) [Figure 3], interface trap density (D_it) [Figure 4], and total interface trap density (D_total) [Figure 5] calculated from capacitance-voltage (C-V) curves [Figure 2] as annealing temperature increased. The acquisition of the lowest Q_eff, D_it, and D_total at 1000°C contributed to the acquisition of the highest breakdown voltage and lowest leakage current density [Figure 6].