ESD protection design for low trigger voltage and high latch-up immunity

Author

Tseng, Jen-Chou ; Hsu, Chung-Ti ; Tsai, Chia-Ku ; Liao, Yu-Ching ; Ker, Ming-Dou

Author_Institution

Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan

fYear

2010

fDate

5-9 July 2010

Firstpage

1

Lastpage

4

Abstract

An embedded silicon-controlled rectifier (SCR) protection structure is proposed with a compatible CMOS layout. It first turns on like a gate-coupled NMOSFET, and then provides second-snapback conduction by a parasitic SCR. As compared with a conventional gate-ground NMOS transistor, the trigger voltage and the human body mode (HBM) test immunity are both greatly improved. Also, this cell is latch-up resistant, both the holding voltage and the turn-on current are adjustable and greatly raised than those of a conventional SCR device.

Keywords

CMOS integrated circuits; electrostatic discharge; thyristors; CMOS layout; ESD protection design; embedded silicon-controlled rectifier protection structure; high latch-up immunity; human body mode test immunity; low trigger voltage; Breakdown voltage; Electrostatic discharge; Humans; Immune system; Immunity testing; Low voltage; MOSFET circuits; Protection; Rectifiers; Thyristors; ESD; device reliability; latch-up;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits (IPFA), 2010 17th IEEE International Symposium on the

Conference_Location

Singapore

ISSN

1946-1542

Print_ISBN

978-1-4244-5596-6

Type

conf

DOI

10.1109/IPFA.2010.5532307

Filename

5532307