Testing FPGA delay faults in the system environment is very different from "ordinary" delay fault testing

Author

Krasniewski, Andrzej

Author_Institution

Inst. of Telecommun., Warsaw Univ. of Technol., Poland

fYear

2001

fDate

2001

Firstpage

37

Lastpage

40

Abstract

Explains differences between testing delay faults in FPGAs and testing delay faults in circuits whose combinational sections can be represented as gate networks. Formulates - in a form suitable for analysis of LUT-based FPGAs - conditions that allow one to check whether or not a given input pair is a test of specific type (non-robust, robust, etc.). The presented theoretical results are shown to simplify an analysis of the various methods for enhancing the effectiveness of detection of FPGA delay faults

Keywords

automatic testing; built-in self test; delays; fault diagnosis; field programmable gate arrays; integrated circuit testing; logic testing; timing; BIST techniques; LUT-based FPGAs; application-dependent self-testing; at-speed testing; combinational sections; delay faults; gate networks; input pair; nonrobust type; robust type; timing-related problems; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Delay estimation; Fault detection; Field programmable gate arrays; Logic testing; System testing; Tellurium;

fLanguage

English

Publisher

ieee

Conference_Titel

On-Line Testing Workshop, 2001. Proceedings. Seventh International

Conference_Location

Taormina

Print_ISBN

0-7695-1290-9

Type

conf

DOI

10.1109/OLT.2001.937815

Filename

937815