Novel fault-tolerant adder design for FPGA-based systems

Author

Alderighi, Monica ; D´Angelo, Sara ; Metra, Cecilia ; Sechi, Giacomo R.

Author_Institution

Ist. di Fisica Cosmica, CNR, Milan, Italy

fYear

2001

fDate

2001

Firstpage

54

Lastpage

58

Abstract

Proposes a novel fault-tolerant adder which is suitable for highly dependable systems implemented by means of field-programmable gate arrays (FPGAs). Compared to alternate conventional designs, the one presented here allows one to achieve fault-tolerance at lower design costs. A prototype has been developed, whose expected behavior has been verified by means of post-layout simulations and experimental measurements. Although our adder has been conceived for FPGA-based systems, it is also suitable to be implemented by means of VLSI and very deep sub-micron technologies

Keywords

VLSI; adders; field programmable gate arrays; integrated circuit design; logic CAD; logic simulation; redundancy; FPGA-based systems; VLSI; design costs; fault-tolerant adder; full-adder block; highly dependable systems; post-layout simulations; triple-modular redundancy; very deep sub-micron technologies; Adders; Circuit faults; Costs; Fault tolerance; Fault tolerant systems; Field programmable gate arrays; Hardware; Noise reduction; Redundancy; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

On-Line Testing Workshop, 2001. Proceedings. Seventh International

Conference_Location

Taormina

Print_ISBN

0-7695-1290-9

Type

conf

DOI

10.1109/OLT.2001.937819

Filename

937819