Automatic bias generation using pipeline instruction state coverage for biased random instruction generation

Biased random instruction generators are commonly used in architectural verification of microprocessors, with biases specified manually by designers. As the complexity of processors grows, so does the complexity of specifying biases. Automatic bias generation speeds up the verification flow and may lead to better coverage of potential design errors. In this work, we present a deterministic algorithm to automatically generate biases that cover all pipeline states, where each pipeline state represents the positions and types of instructions in the pipeline. Test programs generated from these biases can be used for on-line testing in field applications. The quality of the biases generated is evaluated by using them to generate test programs and then simulating the test programs and evaluating various coverage metrics. Experimental results for the PowerPC and ARM7 architectures show that automatically generated biases result in higher design error coverage than random biases and provide better coverage of key architectural features