New reseeding technique for LFSR-based test pattern generation

Author

Kalligeros, E. ; Kavousianos, X. ; Bakalis, D. ; Nikolos, D.

Author_Institution

Dept. of Comput. Eng. & Inf., Patras Univ., Greece

fYear

2001

fDate

2001

Firstpage

80

Lastpage

86

Abstract

Presents a new reseeding technique for LFSR-based test pattern generation suitable for circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the LFSR jumps from a state to the required state (seed) by inverting the logic value of some of the bits of its next state. An efficient algorithm for selecting reseeding points is also presented, which targets complete fault coverage and minimization of the cardinality of the test set and the hardware required for the implementation of the test pattern generator. The application of the proposed technique to ISCAS ´85 and the combinational part of ISCAS ´89 benchmark circuits shows its superiority against the already known reseeding techniques with respect to the length of the test sequence and, in the majority of cases, the hardware required for their implementation

Keywords

automatic test pattern generation; built-in self test; fault diagnosis; integrated circuit testing; logic testing; shift registers; ISCAS ´85 benchmark circuits; ISCAS ´89 benchmark circuits; LFSR-based test pattern generation; cardinality minimization; complete fault coverage; logic value inverting; random-pattern resistant faults; reseeding technique; test sequence length; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Hardware; Integrated circuit testing; Polynomials; Read only memory; System testing; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

On-Line Testing Workshop, 2001. Proceedings. Seventh International

Conference_Location

Taormina

Print_ISBN

0-7695-1290-9

Type

conf

DOI

10.1109/OLT.2001.937823

Filename

937823