Title :
A gated clock scheme for low power scan-based BIST
Author :
Bonhomme, Y. ; Girard, P. ; Guiller, L. ; Landrault, C. ; Pravossoudovitch, S.
Author_Institution :
Lab. d´´Informatique de Robotique et de Microelectronique de Montpellier, Univ. Montpellier II, France
Abstract :
Presents a new low power scan-based BIST technique which can reduce the switching activity during test operation. The proposed low power/energy technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path
Keywords :
automatic testing; boundary scan testing; built-in self test; clocks; logic testing; low-power electronics; clock tree; gated clock scheme; low power technique; scan path; scan-based BIST; switching activity; test operation; Built-in self-test; Circuit testing; Clocks; Costs; Energy consumption; Frequency; Logic circuits; Packaging; Power dissipation; Switches;
Conference_Titel :
On-Line Testing Workshop, 2001. Proceedings. Seventh International
Conference_Location :
Taormina
Print_ISBN :
0-7695-1290-9
DOI :
10.1109/OLT.2001.937824
