Increasing the fault coverage in multiple clock domain systems by using on-line testing of synchronizers

As a result of shrinking minimum feature size, IC clock frequencies are increasing and it is no longer possible, nor desired, to stick to a single clock domain. Multiple-clock domain design will no longer be an isolated design style. This new trend in the industry, referred to as future standard by some companies, poses a lot of test problems due to special modules utilized at the interface between clock domains. These modules are called synchronizers. This paper will present an implementation of the on-line concept on two different synchronizers and it will calculate the probability to detect any stuck-at fault