Title :
Small geometry SOI CMOS cell technology for high density SRAMs
Author :
Hashimoto, M. ; Nagashima, N. ; Miyazawa, Y. ; Shimanoe, M. ; Satoh, H. ; Matsushita, T.
Author_Institution :
Sony Corp., Kanagawa, Japan
Abstract :
The authors report on a full CMOS 4 M SRAM (static RAM) cell using bonded SOI (silicon-on-insulator). The cell area is 21.15 mu m/sup 2/ and the chip area is 129.9 mm/sup 2/. The cell layout is shown, and the cell transfer curves at a Vdd of 1.5 V and 3.3 V are presented. A sufficient noise margin is achieved even at a Vdd of 1.5 V, which is specific to CMOS cells.<>
Keywords :
CMOS integrated circuits; SRAM chips; integrated circuit technology; semiconductor-insulator boundaries; 1.5 V; 3.3 V; 4 Mbit; SOI CMOS cell technology; bonded SOI; cell layout; high density SRAMs; small geometry cell; CMOS technology; Geometry; Isolation technology; Low voltage; MOS devices; Plugs; Random access memory; Ring oscillators; Ultra large scale integration; Wafer bonding;
Conference_Titel :
Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-0243-5
DOI :
10.1109/IEDM.1991.235261
