Title :
A 0.1 mu m-gate elevated source and drain MOSFET fabricated by phase-shifted lithography
Author :
Kimura, S. ; Noda, H. ; Hisamoto, D. ; Takeda, E.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
A novel 0.1- mu m-gate elevated source and drain MOSFET was fabricated utilizing phase-shifted lithography. Phase-shifted lithography enabled less than 0.2- mu m spacing, resulting in a 0.1- mu m gate length in combination with a side-wall oxide film formation technique. It is concluded that the new gate definition process utilizing phase-shifted lithography will be promising for future ultrasmall device fabrication.<>
Keywords :
insulated gate field effect transistors; lithography; semiconductor technology; 0.1 micron; MOSFET; elevated drain; elevated source; gate definition process; phase-shifted lithography; side-wall oxide film formation; submicron gate length; Apertures; Degradation; Electron devices; Fabrication; Laboratories; Lithography; MOSFET circuits; Resists; Substrates; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-0243-5
DOI :
10.1109/IEDM.1991.235269
