DocumentCode :
3301891
Title :
Reliability properties assessment at system level: a co-design framework
Author :
Bolchini, C. ; Pomante, L. ; Salice, F. ; Sciuto, D.
Author_Institution :
Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
fYear :
2001
fDate :
2001
Firstpage :
165
Lastpage :
171
Abstract :
The reliability co-design project aims at integrating in a standard hw/sw co-design flow the elements for achieving a final system able to detect the occurrence of a fault during its operational life. The paper presents the focus of the project, the definition and identification of design methodologies for implementing the nominal, checking and checker functionalities either in hardware or in software. An outline of the system specification and system partitioning aspects is also provided
Keywords :
hardware-software codesign; reliability theory; checker; design methodology; fault detection; hardware-software co-design; system partitioning; system specification; system-level reliability; Costs; Design methodology; Energy consumption; Fault detection; Hardware; Reliability; Space exploration; Time to market; Timing; Yield estimation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
On-Line Testing Workshop, 2001. Proceedings. Seventh International
Conference_Location :
Taormina
Print_ISBN :
0-7695-1290-9
Type :
conf
DOI :
10.1109/OLT.2001.937837
Filename :
937837
Link To Document :
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