Built in self test for low cost testing of a 60MHz synchronous flash memory

Author

Mastrocola, Vincenzo ; Palumbo, Gaetano ; Kumar, Promod ; Pipitone, Francesco ; Introvaia, Giuseppe

Author_Institution

Catania Univ., Italy

fYear

2001

fDate

2001

Firstpage

192

Lastpage

196

Abstract

Describes the application of a methodology of testing, based on an embedded built in self test (BIST) circuitry. Applying the described methodology to a standard flash memory with 60MHz burst read operation option, it is possible to obtain a maximum test coverage at package level, using a low cost automatic test equipment (ATE), with a speed of 20MHz only, commonly used for asynchronous flash memories. In addition, it is possible to extend the use of the BIST during the electrical wafer sort (EWS) test step. This makes possible speed classification at this level and helps to reduce the test time of each read operation, using 5mHz ATE

Keywords

automatic test equipment; built-in self test; flash memories; integrated circuit testing; integrated memory circuits; 20 MHz; 60 MHz; ATE; built in self test; burst read operation; electrical wafer sort; low cost testing; package level; speed classification; synchronous flash memory; test coverage; test time; Automatic testing; Built-in self-test; Circuit testing; Cost function; Flash memory; Frequency; Industrial economics; Packaging; Productivity; Test equipment;

fLanguage

English

Publisher

ieee

Conference_Titel

On-Line Testing Workshop, 2001. Proceedings. Seventh International

Conference_Location

Taormina

Print_ISBN

0-7695-1290-9

Type

conf

DOI

10.1109/OLT.2001.937841

Filename

937841