DocumentCode
3302113
Title
SOI and nanoscale MOSFETs
Author
Chenming Hu
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
2001
fDate
25-27 June 2001
Firstpage
3
Lastpage
4
Abstract
SOI may facilitate the fabrication of two attractive scalable MOSFET structures. Ultra-thin body FET has been demonstrated at 20 nm gate length, using low-barrier silicide S/D, with selectively deposited Ge raised S/D, on bulk substrate, or with Si-Ge channel. FinFET is a simple double gate FET with excellent performance and can be scaled to below 10 nm gate length-a candidate as the ultimate CMOS device. Adjusting the threshold voltage of a device with very thin body is challenging although several novel methods have been suggested.
Keywords
MOSFET; leakage currents; nanotechnology; semiconductor device metallisation; silicon-on-insulator; 20 nm; CMOS; FinFET; SOI; SiGe; double gate FET; gate length; low-barrier silicide S/D region; nanoscale MOSFETs; scalable MOSFET structures; threshold voltage; ultra-thin body FET; FETs; FinFETs; Immune system; MOSFETs; Resistors; Silicon; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Device Research Conference, 2001
Conference_Location
Notre Dame, IN, USA
Print_ISBN
0-7803-7014-7
Type
conf
DOI
10.1109/DRC.2001.937849
Filename
937849
Link To Document