High-K gate dielectrics for sub-100 nm CMOS technology

The materials and processing challenges for the fabrication of high quality, ultra-thin CVD high-K gate stack are reviewed along with the most recent results on CVD ZrO/sub 2/, HfO/sub 2/ and their silicates. The requirement for ultra thin and robust interface layers to avoid any thickness increase due to post-deposition processing to achieve thinnest equivalent oxide thickness (EOT) is discussed. Results are presented on thermal stability of high-K materials, and interfacial reactions of high-K/Si and highK/gate electrode. We also discuss key factors that govern the conduction and degradation mechanisms in high-K gate stack. Both poly-Si and poly-SiGe are explored as possible gate electrode materials and the upper thermal budget limit for such materials is discussed.