DocumentCode :
3302220
Title :
Physical origin of SILC and noisy breakdown in very thin silicon nitride gate dielectric
Author :
Polishchuk, I. ; Tsu-Jae King ; Chenming Hu
fYear :
2001
fDate :
25-27 June 2001
Firstpage :
20
Lastpage :
21
Abstract :
As the equivalent oxide thickness of the MOSFET gate dielectric continues to shrink, the transition to a material with a higher dielectric constant, such as Si/sub 3/N/sub 4/, seems imminent. It is well-recognized that stress-induced leakage current (SILC) and noisy (or soft) breakdown have become very important degradation phenomena in ultra-thin gate dielectrics. A lot of attention has been recently paid to SILC and soft breakdown in SiO/sub 2/ gate dielectrics, however the physical origins of these phenomena have not been thoroughly investigated. An understanding of the physical mechanisms responsible for the degradation of the ultra-thin gate dielectrics is critical to the development of a reliability model for the future generations of CMOS technology. This paper offers for the first time a detailed examination of SILC and noisy breakdown in Si/sub 3/N/sub 4/ demonstrating that these two degradation phenomena have a common origin. The nature of the traps responsible for SILC and noisy breakdown is revealed. The proposed degradation mechanism also provides a key to understanding and modeling of the dielectric reliability in the ultra-thin SiO/sub 2/ and new high-K gate materials.
Keywords :
MISFET; dielectric thin films; interface states; leakage currents; semiconductor device breakdown; semiconductor device models; semiconductor device reliability; semiconductor-insulator boundaries; silicon compounds; tunnelling; CMOS technology; MOSFET gate dielectric; SILC; Si-Si/sub 3/N/sub 4/; Si/sub 3/N/sub 4/ gate dielectric; degradation phenomena; dielectric constant; dielectric reliability; electrical stress; high-K gate materials; interface traps; model; noisy breakdown; offcenter traps; physical mechanisms; reliability model; soft breakdown; stress-induced leakage current; tunnel path; ultra-thin gate dielectrics; very thin gate dielectric; weak conduction paths; CMOS technology; Degradation; Dielectric breakdown; Dielectric materials; Electric breakdown; High K dielectric materials; High-K gate dielectrics; Leakage current; MOSFET circuits; Silicon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Device Research Conference, 2001
Conference_Location :
Notre Dame, IN, USA
Print_ISBN :
0-7803-7014-7
Type :
conf
DOI :
10.1109/DRC.2001.937855
Filename :
937855
Link To Document :
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