High performance of planar double gate MOSFETs with thin backgate dielectrics

Author

Jones, E.C. ; Meikei Ieong ; Kanarsky, T. ; Dokumaci, O. ; Roy, R.A. ; Leathen Shi ; Furukawa, T. ; Miller, R.J. ; Wong, H.S.P.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2001

fDate

25-27 June 2001

Firstpage

28

Lastpage

29

Abstract

Planar double gate CMOS devices with thin silicon channels and electrically separate polysilicon top and bottom gates are fabricated. NFETs with L/sub design/=175 nm and 1.3 mA//spl mu/m and PFETs with L/sub design/=125 nm and 400 /spl mu/A//spl mu/m are achieved at V/sub dd/=1.2 V. To our knowledge, this is the largest current yet achieved in double gate NMOS devices. Electrical results show a high quality backgate dielectric, improvement of SCE using the backgate, and the importance of reducing external resistance in short channel devices.

Keywords

MOSFET; dielectric thin films; elemental semiconductors; semiconductor device measurement; silicon; 1.2 V; 125 nm; 175 nm; NFETs; PFETs; SCE; Si; electrically separate polysilicon gates; external resistance reduction; planar double gate MOSFETs; short-channel effects; thin backgate dielectrics; Annealing; Cobalt; Contact resistance; Contracts; Dielectric devices; Gate leakage; Geometry; MOSFETs; Silicides;

fLanguage

English

Publisher

ieee

Conference_Titel

Device Research Conference, 2001

Conference_Location

Notre Dame, IN, USA

Print_ISBN

0-7803-7014-7

Type

conf

DOI

10.1109/DRC.2001.937859

Filename

937859