A high-level EDA environment for the automatic insertion of HD-BIST structures

Author

Benso, A. ; Cataldo, S. ; Chiusano, S. ; Prinetto, P. ; Zorian, Y.

Author_Institution

Dipt. di Autom. e Inf., Politecnico di Torino, Italy

fYear

1999

fDate

25-28 May 1999

Firstpage

2

Lastpage

6

Abstract

This paper presents a High-Level EDA environment based on the Hierarchical Distributed BIST (HD-BIST), a flexible and reusable approach to solve BIST scheduling issues in system-on-chip applications. HD-BIST allows activating and controlling different BISTed blocks at different levels of hierarchy, with a minimum overhead in terms of area and test time. Besides the hardware layer the authors presented the HD-BIST application layer where a simple modeling language, and a prototypical EDA tool demonstrate the effectiveness of the automation of the HD-BIST insertion in the test strategy definition of a complex system-on-chip.

Keywords

built-in self test; electronic design automation; embedded systems; hardware description languages; hardware-software codesign; integrated circuit testing; simulation languages; BIST scheduling issues; HD-BIST structures; HDML; VHDL; application layer; automatic insertion; embedded cores; hardware layer; hierarchical distributed BIST; high-level EDA environment; minimum overhead; prototypical EDA tool; simple modeling language; system-on-chip applications; test strategy definition; Access protocols; Automatic testing; Built-in self-test; Centralized control; Costs; Electronic design automation and methodology; Hardware; Logic testing; Routing; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

European Test Workshop 1999. Proceedings

Conference_Location

Constance, Germany

Print_ISBN

0-7695-0390-X

Type

conf

DOI

10.1109/ETW.1999.803818

Filename

803818