Single electron transistors with sidewall depletion gates on a silicon-on-insulator quantum wire

For practical application to multi-functional nanoelectronic devices, single electron transistors (SETs) should have controllable and reproducible characteristics. For high temperature operation, recently proposed SET structures have depended on somewhat contingent phenomena such as unintentional potential barriers in quantum wires, e-beam irregularity or randomly distributed nanocrystal arrays, so that their device characteristics couldn´t be predicted. In this work, SETs with sidewall depletion gates on a silicon-on-insulator (SOI) quantum wire have been fabricated by the combination of conventional lithography and VLSI technology, and their properties were investigated.