Isolated uttered words recognition based on GMM/HMM algorithms using SoPC/Nios II processor build on Altera Cyclone II FPGA chip

This paper introduced an approach to design and implement an embedded SoPC (System on a Programmable Chip) technique with Altera Nios II processor for real-time speech recognition system by developing hardware/software with minimum usage of resources (hardware components) and relatively small size software to reduce memory utilization. This is achieved by using Mel Frequency Cepstral Coefficients (MFCCs) technique as speech signal feature extraction (observation vector). Using Gaussian Mixture Model (GMM) to model the observation vector of voice information. Finally, this model passed to the Hidden Markov Model (HMM) as probabilistic model to process the GMM statistically to make decision on utterance words recognition, whether a single or composite, one or more syllable words (i.e. one, six, target). The total framework was implemented on Altera Cyclone II EP2C70F896C6N FPGA chip sitting on ALTERA DE2-70 Development Board. The utility software which are used as tools for design and development hardware/software are Quartus II 11.0sp1 (32-Bit) and Nios II 11.0spl IDE/C++ respectively. Each word model (template) stored as Transition Matrix, Diagonal Covariance Matrices, and Mean Vectors in the system memory. Each word model utilizes only 4.45Kbytes regardless of the spoken word length. Accuracy of the recognition words (digit/0 to digit/10) given 100% for the individual speaker. Training and recognition software has size (code + initialized data) equal to 312Kbytes.