Title :
Non-scan Design-for-testability Of Rt-level Data Paths
Author :
Dey, Sujit ; Potkonjak, Miodrag
Keywords :
Automatic testing; Circuit testing; Design for testability; Flip-flops; Hardware; High level synthesis; Laboratories; National electric code; Permission; Sequential analysis;
Conference_Titel :
Computer-Aided Design, 1994., IEEE/ACM International Conference on
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1994.629889
