DocumentCode
3303244
Title
Non-scan Design-for-testability Of Rt-level Data Paths
Author
Dey, Sujit ; Potkonjak, Miodrag
fYear
1994
fDate
6-10 Nov 1994
Firstpage
640
Lastpage
645
Keywords
Automatic testing; Circuit testing; Design for testability; Flip-flops; Hardware; High level synthesis; Laboratories; National electric code; Permission; Sequential analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1994., IEEE/ACM International Conference on
ISSN
1063-6757
Print_ISBN
0-8186-3010-8
Type
conf
DOI
10.1109/ICCAD.1994.629889
Filename
629889
Link To Document