• DocumentCode
    3303260
  • Title

    Selecting Partial Scan Flip-flops For Circuit Partitioning

  • Author

    Ono, Toshinobu

  • fYear
    1994
  • fDate
    6-10 Nov 1994
  • Firstpage
    646
  • Lastpage
    650
  • Keywords
    Automatic test pattern generation; Circuit testing; Flip-flops; Hardware; National electric code; Partitioning algorithms; Scheduling algorithm; Sequential analysis; Sequential circuits; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1994., IEEE/ACM International Conference on
  • ISSN
    1063-6757
  • Print_ISBN
    0-8186-3010-8
  • Type

    conf

  • DOI
    10.1109/ICCAD.1994.629890
  • Filename
    629890
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3303260