DocumentCode
3303518
Title
Provably Correct High-level Timing Analysis Without Path Sensitization
Author
Bhattacharya, Subhrajit ; Dey, Sujit ; Brglez, Franc
fYear
1994
fDate
6-10 Nov 1994
Firstpage
736
Lastpage
742
Keywords
Circuit analysis; Circuit synthesis; Clocks; Computer science; Delay estimation; Energy consumption; National electric code; Permission; Process design; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1994., IEEE/ACM International Conference on
ISSN
1063-6757
Print_ISBN
0-8186-3010-8
Type
conf
DOI
10.1109/ICCAD.1994.629905
Filename
629905
Link To Document