Title :
A Timing Analysis Algorithm For Circuits With Level-sensitive Latches
Author :
Lee, Jin-Fuw ; Tang, Donald T. ; Wong, C.K.
Keywords :
Algorithm design and analysis; Circuit analysis; Clocks; Constraint optimization; Delay; Flip-flops; Job shop scheduling; Latches; Logic design; Timing;
Conference_Titel :
Computer-Aided Design, 1994., IEEE/ACM International Conference on
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1994.629906
