Mobility based scheduling for the register-transfer synthesis of systolic arrays

The authors present a novel scheduling and allocation algorithm for both one- and two-dimensional SUs (systolic units). This algorithm works across the PEs (processing elements) of an SU to reduce the number of FUs (functional units) required in an implementation. For the examples presented this technique results in fewer FUs and latches than if individual PEs were synthesized and then combined into an SU. In systolic arrays where the silicon area requirement of each PE is high, interlacing across PEs results in an implementation with a smaller design area. The interlacing (latch, controller, and multiplexer) area increases with interlacing up to a certain point. After this point, increased interlacing actually reduces the number of latches and multiplexers in the design, resulting in a drop in interlacing area. This is because in the proposed design strategy the latches are also interlaced in order to make the most efficient use of silicon