Title :
A self-aligned pocket implantation (SPI) technology for 0,. mu m-dual gate CMOS
Author :
Hori, A. ; Kameyama, S. ; Segawa, M. ; Shimomura, H. ; Ogawa, H.
Author_Institution :
Matsushita Electric Ind. Co. Ltd., Osaka, Japan
Abstract :
A novel self-aligned pocket implantation (SPI) technology has been developed. This technology features a localized ´pocket´ implantation using a gate electrode and TiSi/sub 2/ films as self-aligned masks. The gate polysilicon is patterned by KrF excimer laser lithography. The measured minimum gate length Lg (the physical gate length) is 0.21 mu m. This process provides high punchthrough resistance and high current driving capability while maintaining low impurity concentration in the well (less than 5*10/sup 16/ cm/sup -3/). The drain junction capacitance is decreased by 30% for N-MOSFET, and by 49% for P-MOSFET, compared to conventional LDD (lightly doped drain) devices. It is found that a dual gate CMOS fabricated by the SPI technology achieves high-speed circuit performance.<>
Keywords :
CMOS integrated circuits; integrated circuit technology; ion implantation; photolithography; titanium compounds; 0.2 micron; TiSi/sub 2/ films; drain junction capacitance; dual gate CMOS; excimer laser lithography; gate electrode; gate length; gate polysilicon; high current driving capability; high punchthrough resistance; low impurity concentration; polycrystalline Si; self-aligned masks; self-aligned pocket implantation; silicides; CMOS technology; Capacitance; Circuit optimization; Electrical resistance measurement; Electrodes; Impurities; Laser theory; Length measurement; Lithography; MOSFET circuits;
Conference_Titel :
Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-0243-5
DOI :
10.1109/IEDM.1991.235390
