A RISC processor based architecture for control and evaluation of grasping and manipulation with dexterous hands

Author

Kircanski, N. ; Goldenberg, A. ; Zhou, C.

Author_Institution

Dept. of Mech. Eng., Toronto Univ., Ont., Canada

Volume

2

fYear

1993

fDate

19-21 May 1993

Firstpage

463

Abstract

The authors describe the computer architecture for the IRIS Facility, a versatile, multi-degree-of-freedom reconfigurable and expandable setup for research in grasping and manipulation. The proposed computer architecture involves powerful 10 MFLOPS RISC (reduced instruction set computer) processor nodes and a fast point-to-point communication network. Each node includes a host computer and parallel input/output modules. The nodes are controlled by nearly zero-overhead customized real-time OS kernels responsible for task scheduling, communication, and user-interface

Keywords

floating point arithmetic; manipulators; network operating systems; parallel architectures; processor scheduling; real-time systems; reconfigurable architectures; reduced instruction set computing; user interfaces; 10 MFLOPS; IRIS Facility; RISC processor based architecture; customized real-time OS kernels; dexterous hands; grasping; host computer; manipulation; parallel input/output modules; point-to-point communication network; reduced instruction set computer; task scheduling; user-interface; Communication networks; Communication system control; Computer aided instruction; Computer architecture; Computer networks; Concurrent computing; Iris; Kernel; Operating systems; Reduced instruction set computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Computers and Signal Processing, 1993., IEEE Pacific Rim Conference on

Conference_Location

Victoria, BC

Print_ISBN

0-7803-0971-5

Type

conf

DOI

10.1109/PACRIM.1993.407321

Filename

407321