Design of irregular LDPC codec on a single chip FPGA

A novel implementation of irregular low density parity check (LDPC) codec on a single chip Xilinx FPGA is presented in this paper. The encoder and decoder are accomplished by partial parallel architectures with very low complexity. Specifically, details including the decoder and encoder structures, memory management, and required computation units to realize the variable/check node decoding and the parity-check bits generation are discussed. It is verified that the error-correcting capability of the codes with the proposed scheme is kept the same as that by random generation method, while highly parallel encoding/decoding scheme may be realized with ease. Thereby, the proposed design approach for the complex LDPC codec is very promising for real applications.